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CS5463 Single Phase, Bi-directional Power/Energy IC
Features
Energy Data Linearity: 0.1% of Reading over 1000:1 Dynamic Range On-chip Functions:
- Instantaneous Voltage, Current, and Power - IRMS and VRMS, Apparent, Reactive, and Active (Real) Power - Active Fundamental and Harmonic Power - Reactive Fundamental, Power Factor, and Line Frequency - Energy-to-pulse Conversion - System Calibrations and Phase Compensation - Temperature Sensor
Description
The CS5463 is an integrated power measurement device which combines two analog-to-digital converters, power calculation engine, energy-to-frequency converter, and a serial interface on a single chip. It is designed to accurately measure instantaneous current and voltage, and calculate VRMS, IRMS, instantaneous power, apparent power, active power, and reactive power for single-phase, 2- or 3-wire power metering applications. The CS5463 is optimized to interface to shunt resistors or current transformers for current measurement, and to resistive dividers or potential transformers for voltage measurement. The CS5463 features a bi-directional serial interface for communication with a processor and a programmable energy-to-pulse output function. Additional features include on-chip functionality to facilitate system-level calibration, temperature sensor, voltage sag detection, and phase compensation.
ORDERING INFORMATION:
See Page 44.
VD+
Meets accuracy spec for IEC, ANSI, JIS. Low Power Consumption Current Input Optimized for Sense Resistor. GND-referenced Signals with Single Supply On-chip 2.5 V Reference (25 ppm/C typ) Power Supply Monitor Simple Three-wire Digital Serial Interface "Auto-boot" Mode from Serial E2PROM Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
VA+
RESET
IIN+ IIN-
PGA
4th Order Modulator
Digital Filter
HPF Option
MODE
CS SDI
VREFIN
x1
Temperature Sensor
Power Calculation Engine
Serial Interface
SDO SCLK INT
VIN+ VIN-
x10
2nd Order Modulator
Digital Filter
HPF Option
E-to-F
E1 E2 E3
VREFOUT
Voltage Reference
Power Monitor
System Clock
/K
Clock Generator
Calibration
AGND
PFMON
XIN XOUT CPUCLK
DGND
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
AUG `05 DS678PP1
CS5463
TABLE OF CONTENTS
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Voltage Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.2 Current Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 17
5.5.1 Active Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Apparent Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Reactive Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Voltage Channel Sign Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 PFMON Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.6 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Sag and Fault Detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 18 18 18 19 19
19 19 20 20 20 20 21
5.12.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.13 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.13.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.14 Register Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.1 Start Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.2 SYNC0 and SYNC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.3 Power-up/Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.4 Power-down and Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.5 Register Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.6 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Configuration Register ( Config ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Current and Voltage DC Offset Register ( IDCoff , VDCoff ) . . . . . . . . . . . . 6.1.3 Current and Voltage Gain Register ( Ign , Vgn ) . . . . . . . . . . . . . . . . . . . . 6.1.4 Cycle Count Register ( Cycle Count ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5 PulseRateE Register ( PulseRateE ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6 Instantaneous Current, Voltage, and Power Registers ( I , V , P ) . . . . . . 6.1.7 Active (Real) Power Register ( PActive ) . . . . . . . . . . . . . . . . . . . . . . . . . .
2
22 23 23 23 23 23 24 25 26 26 27 27 27 27 28 28
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6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CS5463
6.1.8 RMS Current & Voltage Registers ( IRMS , VRMS ) . . . . . . . . . . . . . . . . . . 6.1.9 Epsilon Register ( ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.10 Power Offset Register ( Poff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.11 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . 6.1.12 Current and Voltage AC Offset Register ( VACoff , IACoff ) . . . . . . . . . . . 6.1.13 Operational Mode Register ( Mode ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.14 Temperature Register ( T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.15 Average and Instantaneous Reactive Power Register ( QAVG , Q ) . . . . 6.1.16 Peak Current and Peak Voltage Register ( Ipeak , Vpeak ) . . . . . . . . . . . . 6.1.17 Reactive Power Register ( QTrig ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.18 Power Factor Register ( PF ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.19 Apparent Power Register ( S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.20 Control Register ( Ctrl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.21 Harmonic Active Power Register ( PH ) . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.22 Fundamental Active Power Register ( PF ) . . . . . . . . . . . . . . . . . . . . . . 6.1.23 Fundamental Reactive Power Register ( QH ) . . . . . . . . . . . . . . . . . . . . 6.1.24 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Temperature Gain Register ( TGain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Temperature Offset Register ( TOff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Voltage Sag and Current Fault Duration Registers ( VSAGDuration , ISAGDuration ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Voltage Sag and Current Fault Level Registers ( VSAGLevel , ISAGLevel ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 29 29 30 30 31 31 31 32 32 32 33 33 33 34 34 34 34 34 35 35 35
7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . . 7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 7.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 7.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . .
36 36 36 36 37 37 37 38 38
8. Auto-boot Mode Using E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 Auto-boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.2 Auto-boot Data for E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.3 Which E2PROMs Can Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40 43 44 44 44
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CS5463
LIST OF FIGURES
Figure 1. CS5463 Read and Write Timing Diagrams.................................................................. 12 Figure 2. Timing Diagram for E1, E2 and E3 ............................................................................... 13 Figure 3. Data Measurement Flow Diagram. .............................................................................. 14 Figure 4. Power Calculation Flow. .............................................................................................. 15 Figure 5. Active and Reactive energy pulse outputs................................................................... 17 Figure 6. Apparent energy pulse outputs .................................................................................... 18 Figure 7. Voltage Channel Sign Pulse outputs ........................................................................... 18 Figure 8. PFMON output to pin E3 .............................................................................................. 19 Figure 9. Sag and Fault Detect ................................................................................................... 19 Figure 10. Oscillator Connection................................................................................................. 20 Figure 11. CS5463 Memory Map ................................................................................................ 22 Figure 12. Calibration Data Flow ................................................................................................ 36 Figure 13. System Calibration of Offset ...................................................................................... 36 Figure 14. System Calibration of Gain. ....................................................................................... 37 Figure 15. Example of AC Gain Calibration ................................................................................ 37 Figure 16. Example of AC Gain Calibration ................................................................................ 37 Figure 17. Typical Interface of E2PROM to CS5463................................................................... 39 Figure 18. Typical Connection Diagram (Single-phase, 2-wire - Direct Connect to Power Line)40 Figure 20. Typical Connection Diagram (Single-phase, 3-wire).................................................. 41 Figure 19. Typical Connection Diagram (Single-phase, 2-wire - Isolated from Power Line)...... 41 Figure 21. Typical Connection Diagram (Single-phase, 3-wire - No Neutral Available)............. 42
LIST OF TABLES
Table 1. Current Channel PGA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2. E2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3. E3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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CS5463
1. OVERVIEW
The CS5463 is a CMOS monolithic power measurement device with a computation engine and an energy-to-frequency pulse output. The CS5463 combines a programmable gain amplifier, two Analog-to-Digital Converters (ADCs), system calibration and a computation engine on a single chip. The CS5463 is designed for power measurement applications and is optimized to interface to a current sense resistor or transformer for current measurement, and to a resistive divider or potential transformer for voltage measurement. The current channel provides programmable gains to accommodate various input levels from a multitude of sensing elements. With single +5 V supply on VA+/AGND, both of the CS5463's input channels can accommodate common mode plus signal levels between (AGND - 0.25 V) and VA+. The CS5463 also is equipped with a computation engine that calculates instantaneous power, IRMS, VRMS, apparent power, active (real) power, reactive power, harmonic active power, active and reactive fundamental power, and power factor. The CS5463 additional features include line frequency, current and voltage sag detection, zero-cross detection, positive-only accumulation mode, and three programmable pulse output pins. To facilitate communication to a microprocessor, the CS5463 includes a simple three-wire serial interface which is SPITM and MicrowireTM compatible. The CS5463 provides three outputs for energy registration. E1, E2 and E3 are designed to interface to a microprocessor.
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2. PIN DESCRIPTION
Crystal Out CPU Clock Output Positive Digital Supply Digital Ground Serial Clock Serial Data Ouput Chip Select Mode Select Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input
Clock Generator Crystal Out Crystal In CPU Clock Output Control Pins and Serial Data I/O Serial Clock Input Serial Data Output Chip Select Mode Select Energy Output 5 6 7 8
SCLK - A Schmitt-Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of the transmit buffer onto the SDO pin when CS is low. SDO -Serial port data output pin.SDO is forced into a high-impedance state when CS is high. CS - Low, activates the serial port interface. MODE - High, enables the "auto-boot" mode. The mode pin has an internal pull-down resistor. figurable outputs for active, apparent, and reactive power, negative energy indication, zero cross detection, and power failure monitoring. E1, E2, E3 outputs are configured in the Operational Modes Register.
XOUT CPUCLK VD+ DGND SCLK SDO CS MODE VIN+ VINVREFOUT VREFIN
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
XIN SDI E2 E1 INT RESET E3 PFMON IIN+ IINVA+ AGND
Crystal In Serial Data Input Energy Output 2 Energy Output 1 Interrupt Reset High Frequency Energy Output Power Fail Monitor Differential Current Input Differential Current Input Positive Analog Supply Analog Ground
1,24
XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
2
18,21,22 E3, E1, E2 - Active-low pulses with an output frequency proportional to the selected power. Con-
Reset Interrupt Serial Data Input Analog Inputs/Outputs Differential Voltage Inputs Differential Current Inputs Voltage Reference Output Voltage Reference Input Power Supply Connections Positive Digital Supply Digital Ground Positive Analog Supply Analog Ground Power Fail Monitor
19 20 23 9,10 15,16 11 12 3 4 14 13
RESET - A Schmitt-Trigger input pin. Low activates Reset, all internal registers (some of which drive output pins) are set to their default states. INT - Low, indicates that an enabled event has occurred. SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.
VIN+, VIN- - Differential analog input pins for the voltage channel. IIN+, IIN- - Differential analog input pins for the current channel. VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magnitude of 2.5 V and is referenced to the AGND pin on the converter. VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.
VD+ - The positive digital supply. DGND - Digital Ground. VA+ - The positive analog supply. AGND - Analog ground. PFMON - The power fail monitor pin monitors the analog supply. If the analog supply does not meet or falls below PFMON's voltage threshold, a Low-supply Detect (LSD) event is set in the status register.
17
6
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3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Voltage Reference Specified Temperature Range Symbol VD+ VA+ VREFIN TA Min 3.135 4.75 -40 Typ 5.0 5.0 2.5 Max 5.25 5.25 +85 Unit V V V C
ANALOG CHARACTERISTICS
* * * *
Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 5 V 5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V. MCLK = 4.096 MHz.
Parameter
Accuracy
Symbol PActive QAvg PF
Min
Typ
Max
Unit
Active Power (Note 1) Average Reactive Power (Note 1 and 2) Power Factor (Note 1 and 2) Current RMS (Note 1) Voltage RMS (Note 1)
Analog Inputs (Both Channels)
All Gain Ranges Input Range 0.1% - 100% All Gain Ranges Input Range 0.1% - 100% All Gain Ranges Input Range 1.0% - 100% Input Range 0.1% - 1.0% All Gain Ranges Input Range 1.0% - 100% Input Range 0.1% - 1.0% All Gain Ranges Input Range 5% - 100% (DC, 50, 60 Hz) All Gain Ranges (Gain = 10) (Gain = 50) (Gain = 50) (50, 60 Hz) (Gain = 10) (Gain = 50) (Gain = 10) (Gain = 50) (Note 3)
-
0.1 0.2 0.2 0.27 0.1 0.17 0.1 500 100 94 -115 32 52 4.0 0.4
VA+ 22.5 4.5 -
% % % % % % % % dB V mVP-P mVP-P dB dB pF pF k Vrms Vrms V/C %
IRMS VRMS
80 -0.25 80 30 -
Common Mode Rejection Common Mode + Signal
Analog Inputs (Current Channel)
CMRR
Differential Input Range [(IIN+) - (IIN-)] Total Harmonic Distortion Crosstalk with Voltage Channel at Full Scale Input Capacitance Effective Input Impedance Noise (Referred to Input) Offset Drift (Without the High Pass Filter) Gain Error
IIN THD IC EII NI OD GE
Notes: 1. Applies when the HPF option is enabled. 2. Applies when the line frequency is equal to the product of the Output Word Rate (OWR) and the value of epsilon ().
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ANALOG CHARACTERISTICS (Continued)
Parameter
Analog Inputs (Voltage Channel)
Symbol [(VIN+) - (VIN-)] VIN THD IC EII NV OD GE T PSCA PSCD PSCD PC
Min 65 2 45 70 2.3 -
Typ 500 75 -70 0.2 16.0 3.0 5 1.3 2.9 1.7 21 11.6 8 10 65 75 2.45 2.55
Max 140 -
Unit mVP-P dB dB pF M Vrms V/C % C mA mA mA mW mW mW W dB dB V V
Differential Input Range
Total Harmonic Distortion Crosstalk with Current Channel at Full Scale (50, 60 Hz) Input Capacitance All Gain Ranges Effective Input Impedance Noise (Referred to Input) Offset Drift (Without the High Pass Filter) Gain Error
Temperature Channel
(Note 3)
Temperature Accuracy
Power Supplies
29 17.5 2.7
Power Supply Currents (Active State) IA+ ID+ (VA+ = VD+ = 5 V) ID+ (VA+ = 5 V, VD+ = 3.3 V) Power Consumption Active State (VA+ = VD+ = 5 V) (Note 4) Active State (VA+ = 5 V, VD+ = 3.3 V) Stand-by State Sleep State Power Supply Rejection Ratio (50, 60 Hz) (Note 5) Voltage Channel Current Channel PFMON Low-voltage Trigger Threshold (Note 6) PFMON High-voltage Power-on Trip Point (Note 7) Notes: 3. Applies before system calibration. 4. All outputs unloaded. All inputs CMOS level.
PSRR PMLO PMHI
5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to AGND. Then the CS5463 is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):
150 PSRR = 20 log --------V eq
6. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1. 7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at which the LSD bit can be permanently reset back to 0.
8
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CS5463
VOLTAGE REFERENCE
Parameter
Reference Output
Symbol VREFOUT (Note 8) (Note 9) TCVREF VR VREFIN
Min +2.4 +2.4 -
Typ +2.5 25 6 +2.5 4 25
Max +2.6 60 10 +2.6 -
Unit V ppm/C mV V pF nA
Output Voltage Temperature Coefficient Load Regulation
Reference Input
Input Voltage Range Input Capacitance Input CVF Current
Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the following formula is used to calculate the VREFOUT Temperature Coefficient:.
TC VREF =
6 A MAX
9. Specified at maximum recommended output of 1 A, source or sink.
DIGITAL CHARACTERISTICS
* * * *
Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 5V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V. MCLK = 4.096 MHz.
Parameter
Master Clock Characteristics
Symbol
Min 2.5 40 40 -2.8 -
Master Clock Frequency Master Clock Duty Cycle CPUCLK Duty Cycle
Filter Characteristics
Internal Gate Oscillator (Note 11) MCLK (Note 12 and 13) (Voltage Channel, 60 Hz) DCLK = MCLK/K (Both Channels) -3 dB (Note 15) VIH OWR
4.096 DCLK/8 DCLK/1024 0.5 1.0
Phase Compensation Range Input Sampling Rate Digital Filter Output Word Rate High-pass Filter Corner Frequency
25
Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR Channel-to-channel Time-shift Error
Input/Output Characteristics
High-level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET Low-level Input Voltage (VD = 5 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET
0.6 VD+ (VD+) - 0.5 0.8 VD+ -
VIL
DS678PP1
(
Typ Max 20 60 60 +2.8 100 Unit MHz % % Hz Hz Hz %F.S. s 0.8 1.5 0.2 VD+ V V V V V V 9
(
VREFOUTMIN) ( (VREFOUTMAX - UTAVG (T VREFO
1 - T AM IN
( 1.0 x 10
(
CS5463
Parameter Low-level Input Voltage (VD = 3.3 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET High-level Output Voltage Low-level Output Voltage Input Leakage Current 3-state Leakage Current Digital Output Pin Capacitance Iout = +5 mA Iout = -5 mA Symbol VIL Min (VD+) - 1.0 Typ 1 5 Max 0.48 0.3 0.2 VD+ 0.4 10 10 Unit V V V V V A A pF
VOH VOL Iin IOZ Cout
Notes: 10. All measurements performed under static conditions. 11. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.
12. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification. 13. The frequency of CPUCLK is equal to MCLK. 14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the full-scale signal applied to the channel input. 15. Configuration Register bits PC[6:0] are set to "0000000".
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CS5463
SWITCHING CHARACTERISTICS
* * * * Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = 5 V 5% VD+ = 3.3 V 5% or 5 V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter Rise Times (Note 16) Fall Times (Note 16)
Start-up
Symbol trise
Min 200 200 50 50 100 -
Typ 50 50 60 20 20 20 8 8
Max 1.0 100 1.0 100 2 50 50 50
Unit s s ns s s ns ms MHz ns ns ns ns ns ns ns ns MCLK MCLK ns MCLK
Any Digital Input Except SCLK SCLK Any Digital Output Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 4.096 MHz (Note 17)
tfall
Oscillator Start-up Time
Serial Port Timing
tost SCLK
Serial Clock Frequency Serial Clock
SDI Timing
Pulse Width High Pulse Width Low
t1 t2 t3 t4 t5 t6 t7 t8
CS Falling to SCLK Rising Data Set-up Time Prior to SCLK Rising Data Hold Time After SCLK Rising
SDO Timing
CS Falling to SDI Driving SCLK Falling to New Data Bit (hold time) CS Rising to SDO Hi-Z
Auto-Boot Timing
Serial Clock MODE setup time to RESET Rising RESET rising to CS falling CS falling to SCLK rising SCLK falling to CS rising
Pulse Width Low Pulse Width High
t9 t10 t11 t12 t13 t14 t15 t16 50 100 50 48 100
8 16
MCLK MCLK ns ns
CS rising to driving MODE low (to end auto-boot sequence). SDO guaranteed setup time to SCLK rising
Notes: 16. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.
DS678PP1
11
CS5463
t3
CS
t1 t2
SC LK
t4
MSB-1 MSB-1 MSB MSB
t5
MSB-1 MSB-1 MSB MSB LSB LSB LSB
SDI
C o m m a n d T im e 8 S C L K s
LSB
H ig h B y te
M id B y te
L o w B y te
SDI Write Timing (Not to Scale)
CS
t6
MSB-1 MSB
H ig h B y t e
MSB-1 MSB LSB
M id B y t e
MSB-1 MSB LSB
L o w B y te
LSB
t8
SDO
UNKNOW N
t1 t2
t7
SC LK
MSB-1
MSB
SDI
C o m m a n d T im e 8 S C L K s
LSB
SYNC0 or SYNC1 Com m and
SYNC0 or SYNC1 Com m and
SYNC0 or SYNC1 Com m and
SDO Read Timing (Not to Scale)
t11
t15
MODE
( IN P U T )
RESET
( IN P U T )
t12 t13 t7
t14
CS
(O U T P U T )
SCLK
(O U T P U T )
t10
t16
t9
t4
t5
SDO
(O U T P U T )
STOP bit
SDI
( IN P U T )
Last 8 B it s
D a ta fro m E E P R O M
Auto-boot Sequence Timing (Not to Scale)
Figure 1. CS5463 Read and Write Timing Diagrams
12
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CS5463
SWITCHING CHARACTERISTICS (Continued)
Parameter E1, E2 and E3 Timing (Note 18 and 19) Period Pulse Width Rising Edge to Falling Edge E2 Setup to E1 and/or E3 Falling Edge E1 Falling Edge to E3 Falling Edge tperiod tpw t3 t4 t5 250 244 6 1.5 248 s s s s s Symbol Min Typ Max Unit
Notes: 18. Pulse output timing is specified at MCLK = 4.096 MHz, E2MODE = 0 and E3MODE1:0 = 0. Refer to Section 5.5 Energy Pulse Output on page 17 for more information on pulse output pins. 19. Timing is proportional to the frequency of MCLK.
E1 E2
tpw t4 t4
tperiod t3 tpw t5 tperiod t3 t5
E3
Figure 2. Timing Diagram for E1, E2 and E3
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Power Supplies (Notes 20 and 21) Positive Digital Positive Analog (Notes 22, 23, 24) (Note 25) All Analog Pins All Digital Pins Symbol VD+ VA+ IIN IOUT PD VINA VIND TA Tstg Min -0.3 -0.3 - 0.3 -0.3 -40 -65 Typ Max +6.0 +6.0 10 100 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Output Current, Any Pin Except VREFOUT
Notes: 20. VA+ and AGND must satisfy [(VA+) - (AGND)] + 6.0 V. 21. VD+ and AGND must satisfy [(VD+) - (AGND)] + 6.0 V. 22. Applies to all pins including continuous over-voltage conditions at the analog input pins. 23. Transient current of up to 100 mA will not cause SCR latch-up. 24. Maximum DC input current for a power supply pin is 50 mA. 25. Total power dissipation, including all input currents and output currents. DS678PP1 13
CS5463
Digital Filter
VOLTAGE
VDCoff* Vgn *
DELAY REG
MUX
x10
2nd Order Modulator
MUX
DELAY REG
SINC 3
X
IIR
+
+
PMF HPF HPF
V* VQ* X
+
X
+
X
Q*
6
*
SYSGain *
2322
X
PC6 PC5 PC4 PC3 PC2 PC1 PC0 Configuration Register *
...
XVDEL XIDEL VHPF
8 7 6
IHPF
5
IIR
4
321 0
Operational Modes Register *
2
X
P*
MUX
CURRENT
PGA
4th Order Modulator
MUX
SINC 3
DELAY REG
X
DELAY REG
IIR
+
+
X I gn*
HPF PMF
I* * DENOTES REGISTER NAME.
Digital Filter
IDCoff*
Figure 3. Data Measurement Flow Diagram.
4. THEORY OF OPERATION
The CS5463 is a dual-channel analog-to-digital converter (ADC) followed by a computation engine that performs power calculations and energy-to-pulse conversion. The data flow for the voltage and current channel measurement and the power calculation algorithms are depicted in Figure 3 and 4, respectively. The analog inputs are structured with two dedicated channels, voltage and current, then optimized to simplify interfacing to various sensing elements. The voltage-sensing element introduces a voltage waveform on the voltage channel input VIN and is subject to a gain of 10x. A second-order delta-sigma modulator samples the amplified signal for digitization. Simultaneously, the current sensing element introduces a voltage waveform on the current channel input IIN and is subject to the two selectable gains of the programmable gain amplifier (PGA). The amplified signal is sampled by a fourth-order delta-sigma modulator for digitization. Both converters sample at a rate of MCLK/8, the over-sampling provides a wide dynamic range and simplified anti-alias filter design. from the calculated VRMS and I RMS as well as the apparent power. When the optional HPF in either channel is disabled an all-pass filter (APF) is implemented. The APF has an amplitude response that is flat within the channel bandwidth and is used for matching phase in systems where one HPF is engaged.
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC offset adjustment and a gain calibration (See Section 7. System Calibration on page 36). The calibrated measurement is available by reading the instantaneous voltage and current registers The Root Mean Square (RMS in Figure 4) calculations are performed on N instantaneous voltage and current samples, Vn and In respectively (where N is the cycle count), using the formula:
I RMS =
4.1 Digital Filters
The decimating digital filters on both channels are Sinc3 filters followed by 4th-order IIR filters. The single-bit data is passed to the low-pass decimation filter and output at a fixed word rate. The output word is passed to an optional IIR filter to compensate for the magnitude roll-off of the low-pass filtering operation. An optional digital high-pass filter (HPF in Figure 3) removes any DC component from the selected signal path. By removing the DC component from the voltage and/or the current channel, any DC content will also be removed from the calculated active power as well. With both HPFs enabled the DC component will be removed
14
In n=0 -------------------N
N-1
and likewise for VRMS, using Vn. IRMS and VRMS are accessible by register reads, which are updated once every cycle count (referred to as a computational cycle).
4.3 Power Measurements
The instantaneous voltage and current samples are multiplied to obtain the instantaneous power (see Figure 3). The product is then averaged over N conversions to compute active power and is used to drive energy pulse outputs E1. Energy output E2 is selectable, providing an energy sign or a pulse output that is proportional to the apparent power. Energy output E3
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CS5463
VACoff*
V*
X
X
N
N
/N
+
+
X
V RMS*
S*
X
IACoff*
+
I*
X
/N
Energy-to-pulse
+
+
-
QTRIG *
E1
E2
I RMS*
Inverse
X
PF*
P* off
PulseRate *
E3
+
P*
+
Q*

N
N
/N
/N
* PACTIVE
X
* QAVG
*DENOTES REGISTER NAME.
Figure 4. Power Calculation Flow.
provides a pulse output that is proportional to the reactive power or apparent power. Output E3 can also be set to display the sign of the voltage applied to the voltage channel or the PFMON comparator output. The apparent power (S) is the combination of the active power and reactive power, without reference to an impedance phase angle, and is calculated by the CS5463 using the following formula:
S = V RMS x I RMS
quadrature power (Q). The product is then averaged over N conversions, utilizing the formula
N
Qn n=1 Q Avg = -----------------------N
Fundamental active (PF) and reactive (QF) power is calculated by performing a discrete Fourier transform (DFT) at the relevant frequency on the instantaneous voltage (V) and current (I). Epsilon is used to set the frequency of the internal sine (imaginary component) and cosine (real component) waveform generator. The harmonic active power (PH) is calculated by subtracting the fundamental active power (PF) from the active power (PActive). The peak current (Ipeak) and peak voltage (Vpeak) are the instantaneous current and voltage, respectively, with the greatest magnitude detected during the last computation cycle. Active, apparent, reactive and fundamental power are updated every computation cycle.
Power Factor (PF) is the active power (PActive) divided by the apparent power (S)
P Active PF = ----------------S
The sign of the power factor is determined by the active power. The CS5463 calculates the reactive power, QTrig utilizing trigonometric identities, giving the formula
Q Trig =
2 S 2 - P Active
4.4 Linearity Performance
The linearity of the VRMS, I RMS, active, reactive and power-factor power measurements (before calibration) will be within 0.1% of reading over the ranges specified, with respect to the input voltage levels required to cause full-scale readings in the IRMS and VRMS registers. Refer to Accuracy Specifications on page 7. Until the CS5463 is calibrated, the accuracy of the CS5463 (with respect to a reference line-voltage and line-current level on the power mains) is not guaranteed to within 0.1%. (See Section 7. System Calibration on page 36.) The accuracy of the internal calculations can often be improved by selecting a value for the Cycle Count Register that will cause the time duration of one computation cycle to be equal to (or very close to) a whole number of power-line cycles (and N must be greater than or equal to 4000). 15
Average reactive power, QAvg is generated by averaging the voltage multiplied by the current with a 90o phase shift difference between them. The 90o phase shift is realized by applying an IIR digital filter in the voltage channel to obtain quadrature voltage (see Figure 3). This filter will give exactly -90o phase shift across all frequencies, and utilizes epsilon () to achieve unity gain at the line frequency. The instantaneous quadrature voltage (VQ) and current (I) samples are multiplied to obtain the instantaneous DS678PP1
CS5463
5. FUNCTIONAL DESCRIPTION
5.1 Analog Inputs
The CS5463 is equipped with two fully differential input channels. The inputs VIN and IIN are designated as the voltage and current channel inputs, respectively. The full-scale differential input voltage for the current and voltage channel is 250 mVP. The Current Gain Register also allows for an additional programmable gain of up to 4x. If an additional gain is applied to the voltage and/or current channel, the maximum input range should be adjusted accordingly.
5.2 IIR Filters
The current and voltage channel are equipped with a 4th-order IIR filter, that is used to compensate for the magnitude roll-off of the low-pass decimation filter. Operational Mode Register bit IIR engages the IIR filters in both the voltage and current channel.
5.1.1 Voltage Channel
The output of the line voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of the CS5463. The voltage channel is equipped with a 10x fixed gain amplifier. The full-scale signal level that can be applied to the voltage channel is 250 mV. If the input signal is a sine wave the maximum RMS voltage at a gain 10x is:
250mV P 2
5.3 High-pass Filters
By removing the offset from either channel, no error component will be generated at DC when computing the active power. By removing the offset from both channels, no error component will be generated at DC when computing VRMS, IRMS and apparent power. Operational Mode Register bits VHPF and IHPF activate the HPF in the voltage and current channel respectively. When a high-pass filter is engaged in only one channel, an all-pass filter (APF) is applied to the other channel.
-------------------- 176.78mV -
RMS
which is approximately 70.7% of maximum peak voltage. The voltage channel is also equipped with a Voltage Gain Register, allowing for an additional programmable gain of up to 4x.
5.1.2 Current Channel
The output of the current sense resistor or transformer is connected to the IIN+ and IIN- input pins of the CS5463. To accommodate different current sensing elements the current channel incorporates a Programmable Gain Amplifier (PGA) with two programmable input gains. Configuration Register bit Igain (see Table 1) defines the two gain selections and corresponding maximum input signal level.
Igain Maximum Input Range
5.4 Performing Measurements
The CS5463 performs measurements of instantaneous voltage (Vn) and current (In), and calculates instantaneous power (Pn) at an Output Word Rate (OWR) of
( MCLK K ) OWR = ---------------------------1024
where K is the clock divider selected in the Configuration Register. The RMS voltage (VRMS), RMS current (IRMS) and active power (Pactive) are computed, using N instantaneous samples of Vn, In and Pn respectively, where N is the value in the Cycle Count Register and is referred to as a "computation cycle". The apparent power (S) is the product of VRMS and IRMS. A computation cycle is derived from the master clock (MCLK), with frequency:
OWR Computation Cycle = -------------N
0 1
250 mV 50 mV
10x 50x
Table 1. Current Channel PGA Setting
For example, if Igain=0, the current channel's PGA gain is set to 10x. If the input signals are pure sinusoids with zero phase shift, the maximum peak differential signal on the current or voltage channel is 250 mVP. The input signal levels are approximately 70.7% of maximum peak voltage producing a full-scale energy pulse registration equal to 50% of absolute maximum energy pulse registration. This will be discussed further in See Section 5.5 Energy Pulse Output on page 17.
Under default conditions and with K = 1, N = 4000, and MCLK = 4.096 MHz - the OWR = 4000 Hz and the Computation Cycle = 1 Hz. All measurements are available as a percentage of full scale. The format for signed registers is a two's complement, normalized value between -1 and +1. The format
16
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CS5463
for unsigned registers is a normalized value between 0 and 1. A register value of
23 (2 - 1) ----------------------- = 0.99999988 23 2
the pulse output mode, which is controlled by bit E2MODE in the Operational Mode Register. E2MODE 0 1 E2 Output Mode Sign of Energy Apparent Energy
represents the maximum possible value. At each instantaneous measurement, the CRDY bit will be set in the Status Register, and the INT pin will become active if the CRDY bit is unmasked in the Mask Register. At the end of each computation cycle, the DRDY bit will be set in the Status Register, and the INT pin will become active if the DRDY bit is unmasked in the Mask Register. When these bits are asserted, they must be cleared before they can be asserted again. If the Cycle Count Register (N) is set to 1, all output calculations are instantaneous, and DRDY, like CRDY, will indicate when instantaneous measurements are finished. Some calculations are inhibited when the cycle count is less than 2. Epsilon () is the ratio of the input line frequency (fi) to the sample frequency (fs) of the ADC.
Table 2. E2 Pin Configuration The E3 pin can be set to register, Reactive Energy (default), PFMON, Voltage Channel Sign, or Apparent Energy. Table 3 defines the pulse output format, which is controlled by bits E3MODE[1:0] in the Operational Mode Register. E3MODE1 0 0 1 1 E3MODE0 0 1 0 1 E3 OutPut Mode Reactive Energy PFMON Voltage Channel Sign Apparent Energy
Table 3. E3 Pin Configuration The pulse output frequency of E1, E2, and E3 is directly proportional to the power calculated from the input signals. The value contained in the PulseRateE Register is the ratio of the energy-output-pulse per samples at full scale, which defines the average frequency for the output pulses. The pulse width, tpw in Figure 2, is an integer multiple of MCLK cycles approximately equal to:
t pw ( sec )
= fi fs
where fs = MCLK / (K*1024). With MCLK = 4.096 MHz and clock divider K = 1, fs = 4000 Hz. For the two most-common line frequencies, 50 Hz and 60 Hz
and
= 50 Hz 4000 Hz = 0.0125
----------------------------------- ( MCLK/K ) / 1024
1
If MCLK = 4.096 MHz and K = 1 then tpw 0.25 ms.
= 60 Hz 4000 Hz = 0.015
5.5.1 Active Energy
The E1 pin produces active-low pulses with an output frequency proportional to the active power. The E2 pin is the energy direction indicator. Positive energy is represented by E1 pin falling while the E2 is high. Negative energy is represented by the E1 pin falling while the E2 is low. The E1 and E2 switching characteristics are specified in Figure 2. Timing Diagram for E1, E2 and E3 on page13. Figure 5 illustrates the pulse output format with positive active energy and negative reactive energy.
E1 E2
E3
respectively. Epsilon is used to set the frequency of the internal sine/cosine reference for the fundamental active and reactive measurements, and the gain of the 90o phase shift (IIR) filter for the average reactive power.
5.5 Energy Pulse Output
The CS5463 provides three output pins for energy registration. By default, E1 registers active energy, E3 registers reactive energy, and E2 indicates the sign of both active and reactive energy. (See Figure 2. Timing Diagram for E1, E2 and E3 on page13.) The E1 pulse output is designed to register the Active Energy. The E2 pin can be set to register Apparent Energy. Table 2 defines
Figure 5. Active and Reactive energy pulse outputs
DS678PP1
17
CS5463
The pulse output frequency of E1 is directly proportional to the active power calculated from the input signals. To calculate the output frequency on E1, the following transfer function can be utilized: With MCLK = 4.096 MHz and default settings, the pulses will have an average frequency equal to the frequency specified by PulseRate when the input signals applied to the voltage and current channels cause full-scale readings in the instantaneous voltage and current registers. The maximum pulse frequency from the E2 (and/or E3) pin is (MCLK/K)/2048. The E2 (and/or E3) pin outputs apparent energy, but has no energy direction indicator.
FREQ
P
VIN x VGAIN x IIN x IGAIN x PF x PulseRate = -------------------------------------------------------------------------------------------------------------------------------2 VREFIN
FREQP = Average frequency of active energy E1 pulses [Hz] VIN = rms voltage across VIN+ and VIN- [V] VGAIN = Voltage channel gain IIN = rms voltage across IIN+ and IIN- [V] IGAIN = Current channel gain PF = Power Factor PulseRate = PulseRateE x (MCLK/K)/2048 [Hz] VREFIN = Voltage at VREFIN pin [V]
5.5.3 Reactive Energy Mode
Reactive energy pulses are output on pin E3 by setting bit E3MODE1:0 = 0 (default) in the Operational Mode Register. Positive reactive energy is registered by E3 falling when E2 is high. Negative reactive energy is registered by E3 falling when E2 is low. Figure 5 on page 17 illustrates the pulse output format with negative reactive energy output on pin E3 and the sign of the energy on E2. The E3 and E2 pulse output switching characteristics are specified in Figure 2 on page 13. The pulse output frequency of E3 is directly proportional to the reactive power calculated from the input signals. To calculate the output frequency on E3, the following transfer function can be utilized:
VIN x VGAIN x IIN x IGAIN x PQ x PulseRate = --------------------------------------------------------------------------------------------------------------------------------2 VREFIN
With MCLK = 4.096 MHz, PF = 1 and default settings, the pulses will have an average frequency equal to the frequency specified by PulseRate when the input signals applied to the voltage and current channels cause full-scale readings in the instantaneous voltage and current registers. The maximum pulse frequency from the E1 pin is (MCLK/K)/2048.
5.5.2 Apparent Energy Mode
Setting bit E2MODE = 1 in the Operational Mode Register outputs apparent energy pulses on pin E2. Setting bit E3MODE1:0 = 3 in the Operational Mode Register outputs apparent energy pulses on pin E3. Figure 6 illustrates the pulse output format with apparent energy on E2 (E2MODE = 1 and E3MODE1:0 = 0)
E1 E2 E3
FREQ
Q
FREQQ = Average frequency of reactive energy E3 pulses [Hz] VIN = rms voltage across VIN+ and VIN- [V] VGAIN = Voltage channel gain IIN = rms voltage across IIN+ and IIN- [V] IGAIN = Current channel gain PQ = 1 - PF2 PulseRate = PulseRateE x (MCLK/K)/2048 [Hz] VREFIN = Voltage at VREFIN pin [V]
Figure 6. Apparent energy pulse outputs
The pulse output frequency of E2 (and/or E3) is directly proportional to the apparent power calculated from the input signals. Since apparent power is without reference to an impedance phase angle, the following transfer function can be utilized to calculate the output frequency on E2 (and/or E3).
FREQ VIN x VGAIN x IIN x IGAIN x PulseRate = -----------------------------------------------------------------------------------------------------------------S 2 VREFIN
With MCLK = 4.096 MHz, PF = 0 and default settings, the pulses will have an average frequency equal to the frequency specified by PulseRate when the input signals applied to the voltage and current channels cause full-scale readings in the instantaneous voltage and current registers. The maximum pulse frequency from the E1 pin is (MCLK/K)/2048.
5.5.4 Voltage Channel Sign Mode
Setting bit E3MODE1:0 = 2 in the Operational Mode Register outputs the sign of the voltage channel on pin E3. Figure 7 illustrates the output format with voltage channel sign on E3
E1 E2 E3
FREQS = Average frequency of apparent energy E2 and/or E3 pulses [Hz] VIN = rms voltage across VIN+ and VIN- [V] VGAIN = Voltage channel gain IIN = rms voltage across IIN+ and IIN- [V] IGAIN = Current channel gain PulseRate = PulseRateE x (MCLK/K)/2048 [Hz] VREFIN = Voltage at VREFIN pin [V]
Figure 7. Voltage Channel Sign Pulse outputs 18 DS678PP1
CS5463
Output pin E3 is high when the line voltage is positive and pin E3 is low when the line voltage is negative.
5.6 Sag and Fault Detect Feature
Status bit VSAG and IFAULT in the Status Register, indicates a sag occurred in the power line voltage and current, respectively. For a sag condition to be identified, the absolute value of the instantaneous voltage or current must be less than the sag level for more then half of the sag duration (see Figure 9). To activate Voltage Sag detect, a voltage sag level must be specified in the Voltage Sag Level Register (VSAGLevel), and a voltage sag duration must be specified in the Voltage Sag Duration Register (VSAGDuration). To activate Current Fault detect, a current sag level must be specified in the Current Fault Level Register (ISAGLevel), and a current sag duration must be specified in the Current Fault Duration Register (ISAGDuration). The voltage and current sag levels are specified as the average of the absolute instantaneous voltage and current, respectively. Voltage and current sag duration is specified in terms of ADC cycles.
5.5.5 PFMON Output Mode
Setting bit E3MODE1:0 = 1 in the Operational Mode Register outputs the PFMON comparator on pin E3. Figure 8 illustrates the output format with PFMON on E3
E1 E2
E3
Above PFMON Threshold
Below PFMON Threshold
Figure 8. PFMON output to pin E3
When PFMON is greater then the threshold, pin E3 is high and when PFMON is less then the threshold pin E3 is low.
5.5.6 Design Example
EXAMPLE #1:
The maximum rated levels for a power line meter are 250 V rms and 20 A rms. The required number of pulses-per-second on E1 is 100 pulses per second (100 Hz), when the levels on the power line are 220 V rms and 15 A rms. With a 10x gain on the voltage and current channel the maximum input signal is 250 mVP. (See Section 5.1 Analog Inputs on page 16.) To prevent over-driving the channel inputs, the maximum rated rms input levels will register 0.6 in VRMS and IRMS by design. Therefore the voltage level at the channel inputs will be 150 mV rms when the maximum rated levels on the power lines are 250 V rms and 20 A rms. Solving for PulseRate using the transfer function:
2 FREQ P x VREFIN PulseRate = -------------------------------------------------------------------------------------------VIN x VGAIN x IIN x IGAIN x PF
Level
Duration
Figure 9. Sag and Fault Detect
5.7 On-chip Temperature Sensor
The on-chip temperature sensor is designed to assist in characterizing the measurement element over a desired temperature range. Once a temperature characterization is performed, the temperature sensor can then be utilized to assist in compensating for temperature drift. Temperature measurements are performed during continuous conversions and stored in the Temperature Register. The Temperature Register (T) default is Celsius scale (oC). The Temperature Gain Register (Tgain) and Temperature Offset Register (Toff) are constant values allowing for temperature scale conversions.
Therefore with PF = 1 and:
VIN = 220V x ( ( 150mV ) ( 250V ) ) = 132mV IIN = 15A x ( ( 150mV ) ( 20A ) ) = 112.5mV
the pulse rate is:
2 100 x 2.5 PulseRate = ---------------------------------------------------------------- = 420.8754Hz 0.132 x 10 x 0.1125 x 10
and the PulseRateE Register is set to:
PulseRateE = PulseRate --------------------------------------( MCLK K ) 2048 =
0.2104377
with MCLK = 4.096 MHz and K = 1.
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The temperature update rate is a function of the number of ADC samples. With MCLK = 4.096 MHz and K = 1 the update rate is:
--------------------------------------- = ( MCLK K ) 1024
2240 samples 0.56 sec
XOUT C1
Oscillator Circuit
The Cycle Count Register (N) must be set to a value greater then one. Status bit TUP in the Status Register, indicates when the Temperature Register is updated. The Temperature Offset Register sets the zero-degree measurement. To improve temperature measurement accuracy, the zero-degree offset may need to be adjusted after the CS5463 is initialized. Temperature offset calibration is achieved by adjusting the Temperature Offset Register (Toff) by the differential temperature (T) measured from a calibrated digital thermometer and the CS5463 temperature sensor. A one degree adjustment to the Temperature Register (T) is achieved by adding 2.737649x10-4 to the Temperature Offset Register (Toff). Therefore,
T off
XIN C2
DGND
C1 = C2 = 22 pF
Figure 10. Oscillator Connection
5.9 System Initialization
Upon powering up, the digital circuitry is held in reset until the analog voltage reaches 4.0 V. At that time, an eight XIN clock period delay is enabled to allow the oscillator to stabilize. The CS5463 will then initialize. A hardware reset is initiated when the RESET pin is asserted with a minimum pulse width of 50 ns. The RESET signal is asynchronous, with a Schmitt Trigger input. Once the RESET pin is de-asserted, an eight XIN clock period delay is enabled. A software reset is initiated by writing the command 0x80. After a hardware or software reset, the internal registers (some of which drive output pins) will be reset to their default values. Status bit DRDY in the Status Register, indicates the CS5463 is in its active state and ready to receive commands.
=
T
off
+ ( T x 2.737649 10 - 4 )
if Toff = -0.09104831 and T = -7.0 (oC), then
T off
=
- 0.09104831
+ ( -7.0 x 2.737649 10 ) =
-4
- 0.09296466
or 0xF419BC (2's compliment notation) is stored in the Temperature Offset Register (Toff). To convert the Temperature Register (T) from a Celsius scale (oC) to a Fahrenheit scale (oF) utilize the formula
o
9o F = -- ( C + 17.7778 ) 5
Applying the above relationship to the CS5461A temperature measurement algorithm
5.10 Power-down States
The CS5463 has two power-down states, Stand-by and Sleep. In the stand-by state all circuitry except the voltage reference and crystal oscillator is turned off. To return the device to the active state a power-up command is sent to the device. In Sleep state all circuitry except the instruction decoder is turned off. When the power-up command is sent to the device, a system initialization is performed (See Section 5.9 System Initialization on page 20).
-4 o o 9 T F = -- x T gain T C + T off + ( 17.7778 x 2.737649 10 ) 5
If Toff = -0.09296466 and Tgain = 23.799 for a Celsius scale, then the modified values are Toff = -0.08809772 (0xF4B937) and Tgain = 42.8382 (0x55AD29) for a Fahrenheit scale.
5.8 Voltage Reference
The CS5463 is specified for operation with a +2.5 V reference between the VREFIN and AGND pins. To utilize the on-chip 2.5 V reference, connect the VREFOUT pin to the VREFIN pin of the device. The VREFIN can be used to connect external filtering and/or references.
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5.11 Oscillator Characteristics
XIN and XOUT are the input and output of an inverting amplifier configured as an on-chip oscillator, as shown in Figure 10. The oscillator circuit is designed to work with a quartz crystal. To reduce circuit cost, two load capacitors C1 and C2 are integrated in the device, from XIN to DGND, and XOUT to DGND. PCB trace lengths
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should be minimized to reduce stray capacitance. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. The CS5463 can be driven by an external oscillator ranging from 2.5 to 20 MHz, but the K divider value must be set such that the internal MCLK will run somewhere between 2.5 MHz and 5 MHz. The K divider value is set with the K[3:0] bits in the Configuration Register. As an example, if XIN = MCLK = 15 MHz, and K is set to 5, then DCLK is 3 MHz, which is a valid value for DCLK.
INTERRUPT HANDLER ROUTINE:
4) Read the Status Register. 5) Disable all interrupts. 6) Branch to the proper interrupt service routine. 7) Clear the Status Register by writing back the read value in step 4. 8) Re-enable interrupt 9) Return from interrupt service routine. This handshaking procedure ensures that any new interrupts activated between steps 4 and 7 are not lost (cleared) by step 7.
5.12 Event Handler
The INT pin is used to indicate that an internal error or event has taken place in the CS5463. Writing a logic 1 to any bit in the Mask Register allows the corresponding bit in the Status Register to activate the INT pin. The interrupt condition is cleared by writing a logic 1 to the bit that has been set in the Status Register. The behavior of the INT pin is controlled by the IMODE and IINV bits of the Configuration Register.
IMODE IINV INT Pin
5.13 Serial Port Overview
The CS5463 incorporates a serial port transmit and receive buffer with a command decoder that interprets one-byte (8 bits) commands as they are received. There are four types of commands; instructions, synchronizing, register writes and register reads (See Section 5.15 Commands on page 23). Instructions are one byte in length and will interrupt any instruction currently executing. Instructions do not affect register reads currently being transmitted. Synchronizing commands are one byte in length and only affect the serial interface. Synchronizing commands do not affect operations currently in progress. Register writes must be followed by three bytes of data. Register reads can return up to four bytes of data. Commands and data are transferred most-significant bit (MSB) first. Figure 1 on page 12, defines the serial port timing and required sequence necessary to write to and read from the serial port receive and transmit buffer, respectively. While reading data from the serial port, commands and data can be simultaneously written. Starting a new register read command while data is being read will terminate the current read in progress. This is acceptable if the remainder of the current read data is not needed. During data reads, the serial port requires input data. If a new command and data is not sent, SYNC0 or SYNC1 must be sent.
0 0 1 1
0 1 0 1
Active-low Level Active-high Level Low Pulse High Pulse
Table 4. Interrupt Configuration
If the interrupt output signal format is set for either falling or rising edge, the duration of the INT pulse will be at least one DCLK cycle (DCLK = MCLK/K).
5.12.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
INITIALIZATION:
5.13.1 Serial Port Interface
The serial port interface is a "4-wire" synchronous serial communications interface. The interface is enabled to start excepting SCLKs when CS (Chip Select) is asserted. SCLK (Serial bit-clock) is a Schmitt-trigger input that is used to strobe the data on SDI (Serial Data In) into the receive buffer and out of the transmit buffer onto SDO (Serial Data Out).
1) All Status bits are cleared by writing 0xFFFFFF to the Status Register. 2) The condition bits which will be used to generate interrupts are then set to logic 1 in the Mask Register. 3) Enable interrupts.
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If the serial port interface becomes unsynchronized with respect to the SCLK input, any attempt to clock valid commands into the serial interface may result in unexpected operation. The serial port interface must then be re-initialized by one of the following actions: Drive the CS pin high, then low. Hardware Reset (drive RESET pin low, for at least 10 s). Issue the Serial Port Initialization Sequence, which is 3 (or more) SYNC1 command bytes (0xFF) followed by one SYNC0 command byte (0xFE).
0x800 0x7FF
registers in another page, the Page Register (address 0x1F) must be written with the desired page number.
0xFFF
ROM 2048 Words
Pages 0x40 - 0x7F
If a re-synchronization is necessary, it is best to re-initialize the part either by hardware or software reset (0x80), as the state of the part may be unknown.
Hardware Registers* 32 Pages
0x400 0x3FF
Pages 0x20 - 0x3F
5.14 Register Paging
Read/write commands access one of the 32 registers within a specified page. By default, Page = 0. To access
0x000
Software Register* 32 Pages
Pages 0 - 0x1F
* Accessed using register read/write commands.
Figure 11. CS5463 Memory Map
Example: Reading register 6 in page 3. 1. Write 3 to page register with command and data: 0x7E 0x00 0x00 0x03 2. Read register 6 with command: 0x0C 0xFF 0xFF 0xFF
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5.15 Commands
All commands are 8-bits in length. Any byte that is not listed in this section is invalid. Commands that write to registers must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent which can execute during the original read). All commands except register reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.15.1 Start Conversions
B7 1 B6 1 B5 1 B4 0 B3 C3 B2 0 B1 0 B0 0
Initiates acquiring measurements and calculating results. The device has two modes of acquisition. C3 Modes of acquisition/measurement 0 = Perform a single computation cycle 1 = Perform continuous computation cycles
5.15.2 SYNC0 and SYNC1
B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 SYNC
The serial port can be initialized by asserting CS or by sending three or more consecutive SYNC1 commands followed by a SYNC0 command. The SYNC0 or SYNC1 can also be sent while sending data out. SYNC 0 = Last byte of a serial port re-initialization sequence. 1 = Used during reads and serial port initialization.
5.15.3 Power-up/Halt
B7 1 B6 0 B5 1 B4 0 B3 0 B2 0 B1 0 B0 0
If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all computations will be halted.
5.15.4 Power-down and Software Reset
B7 1 B6 0 B5 0 B4 S1 B3 S0 B2 0 B1 0 B0 0
To conserve power the CS5463 has two power-down states. In stand-by state all circuitry, except the analog/digital clock generators, is turned off. In the sleep state all circuitry, except the command decoder, is turned off. Bringing the CS5463 out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog oscillator. S[1:0] Power-down state 00 = Software Reset 01 = Halt and enter stand-by power saving state. This state allows quick power-on 10 = Halt and enter sleep power saving state. 11 = Reserved
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5.15.5 Register Read/Write
B7 0 B6 W/R B5 RA4 B4 RA3 B3 RA2 B2 RA1 B1 RA0 B0 0
The Read/Write informs the command decoder that a register access is required. During a read operation, the addressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is clocked into an input buffer and transferred to the addressed register upon completion of the 24th SCLK. W/R Write/Read control 0 = Read 1 = Write Register address bits (bits 5 through 1) of the read/write command.
RA[4:0]
Register Page 0
Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10101 10111 11000 11001 11010 11011 11100 11101 11110 11111
Name Config IDCoff Ign VDCoff Vgn Cycle Count PulseRateE I V P Pactive IRMS VRMS (Epsilon) Poff Status IACoff VACoff Mode T QAVG Q IPeak VPeak QTrig PF Mask S Ctrl PH PF QF
Description Configuration Current DC Offset Current Gain Voltage DC Offset Voltage Gain Number of A/D conversions used in one computation cycle (N)). Sets the E1, E2 and E3 energy-to-frequency output pulse rate. Instantaneous Current Instantaneous Voltage Instantaneous Power Active (Real) Power RMS Current RMS Voltage Ratio of line frequency to output word rate (OWR) Power Offset Status Current AC (RMS) Offset Voltage AC (RMS) Offset Operation Mode Temperature Average Reactive Power Instantaneous Reactive Power Peak Current Peak Voltage Reactive Power calculated from Power Triangle Power Factor Interrupt Mask Apparent Power Control Harmonic Active Power Fundamental Active Power Fundamental Reactive Power / Page
Note: For proper operation, do not attempt to write to unspecified registers.
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Register Page 1
Address 2 3
RA[4:0] 00010 00011
Name TGain Toff
Description Temperature Sensor Gain Temperature Sensor Offset
Register Page 3
Address 6 7 10 11
RA[4:0] 00110 00111 01010 01011
Name VSAGDuration VSAGLevel ISAGDuration ISAGLevel
Description Voltage sag sample interval Voltage sag level Current fault sample interval Current fault level
Note: For proper operation, do not attempt to write to unspecified registers.
5.15.6 Calibration
B7 1 B6 1 B5 0 B4 CAL4 B3 CAL3 B2 CAL2 B1 CAL1 B0 CAL0
The CS5463 can perform system calibrations. Proper input signals must be applied to the current and voltage channel before performing a designated calibration. CAL[4:0]* Designates calibration to be performed 01001 = Current channel DC offset 01010 = Current channel DC gain 01101 = Current channel AC offset 01110 = Current channel AC gain 10001 = Voltage channel DC offset 10010 = Voltage channel DC gain 10101 = Voltage channel AC offset 10110 = Voltage channel AC gain 11001 = Current and Voltage channel DC offset 11010 = Current and Voltage channel DC gain 11101 = Current and Voltage channel AC offset 11110 = Current and Voltage channel AC gain
*For proper operation, values for CAL[4:0] not specified should not be used.
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6. REGISTER DESCRIPTION
1. 2. "Default" = bit status after power-on or reset Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Page 0 Registers
6.1.1 Configuration Register ( Config )
Address: 0
23 PC6 15 EWA 7 22 PC5 14 6 21 PC4 13 5 20 PC3 12 IMODE 4 iCPU 19 PC2 11 IINV 3 K3 18 PC1 10 2 K2 17 PC0 9 1 K1 16 Igain 8 0 K0
Default = 0x000001 PC[6:0] Phase compensation. A 2's complement number which sets a delay in the voltage channel relative to the current channel. Default setting is 0000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz). See Section 7.2 Phase Compensation on page 38 for more information. Sets the gain of the current PGA. 0 = Gain is 10 (default) 1 = Gain is 50 Allows the E1 and E2 pins to be configured as open-collector output pins. 0 = Normal outputs (default) 1 = Only the pull-down device of the E1 and E2 pins are active Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt. 00 = Active-low level (default) 01 = Active-high level 10 = High-to-low pulse 11 = Low-to-high pulse Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = Normal operation (default) 1 = Minimize noise when CPUCLK is driving rising edge logic Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of "0000" will set K to 16 (not zero). K = 1 at reset.
Igain
EWA
IMODE, IINV
iCPU
K[3:0]
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6.1.2 Current and Voltage DC Offset Register ( IDCoff , VDCoff )
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default = 0x000000 The DC Offset registers (IDCoff,VDCoff) are initialized to 0.0 on reset. When DC Offset calibration is performed, the register is updated with the DC offset measured over a computation cycle. DRDY will be set at the end of the calibration. This register may be read and stored for future system offset compensation. The value is represented in two's complement notation and in the range of -1.0 IDCoff, VDCoff < 1.0, with the binary point to the right of the MSB. See Section 7.1.2.1 DC Offset Calibration Sequence on page 36 for more information.
6.1.3 Current and Voltage Gain Register ( Ign , Vgn )
Address: 2 (Current Gain); 4 (Voltage Gain)
MSB 21 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 LSB 2-22
Default = 0x400000 = 1.000 The gain registers (Ign,Vgn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed, the register is updated with the gain measured over a computation cycle. DRDY will be set at the end of the calibration. This register may be read and stored for future system gain compensation. The value is in the range 0.0 Ign,Vgn < 3.9999, with the binary point to the right of the second MSB.
6.1.4 Cycle Count Register ( Cycle Count )
Address: 5
MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20
Default = 0x000FA0 = 4000 Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024N). A one second computational cycle period occurs when MCLK = 4.096 MHz, K = 1, and N = 4000.
6.1.5 PulseRateE Register ( PulseRateE )
Address: 6
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)
PulseRateE sets the frequency of E1, E2, & E3 pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's complement notation and in the range is -1.0 PulseRateE < 1.0, with the binary point to the right of the MSB. Negative values have the same effect as positive. See Section 5.5 Energy Pulse Output on page 17 for more information.
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6.1.6 Instantaneous Current, Voltage, and Power Registers ( I , V , P )
Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage); 9 (Instantaneous Power)
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous voltage and current samples are multiplied to obtain Instantaneous Power (P). The value is represented in two's complement notation and in the range of -1.0 I, V, P < 1.0, with the binary point to the right of the MSB.
6.1.7 Active (Real) Power Register ( PActive )
Address: 10 (Active Power)
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power (PActive). The value will be within in the range of -1.0 PActive< 1.0. The value is represented in two's complement notation, with the binary point to the right of the MSB.
6.1.8 RMS Current & Voltage Registers ( IRMS , VRMS )
Address: 11 (IRMS); 12 (VRMS)
2-2 2-3 2-4 2-5 MSB 2-1 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 LSB 2-24
IRMS and VRMS contain the Root Mean Square (RMS) values of I and V, calculated each computation cycle. The value is represented in unsigned binary notation and in the range of 0.0 IRMS, VRMS < 1.0, with the binary point to the left of the MSB.
6.1.9 Epsilon Register ( )
Address: 13
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default = 0x01999A = 0.0125 sec Epsilon () is the ratio of the input line frequency to the sample frequency of the ADC (See Section 5.4 Performing Measurements on page 16). Epsilon is either written to the register, or measured during conversions. The value is represented in two's complement notation and in the range of -1.0 < 1.0, with the binary point to the right of the MSB. Negative values have no significance.
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6.1.10 Power Offset Register ( Poff )
Address: 14
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default = 0x000000 Power Offset (Poff) is added to the instantaneous power being accumulated in the Pactive register, and can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system. The value is represented in two's complement notation and in the range of -1.0 Poff < 1.0, with the binary point to the right of the MSB.
6.1.11 Status Register and Mask Register ( Status , Mask )
Address: 15 (Status Register); 26 (Mask Register)
23 DRDY 15 7 TUP 22 14 IROR 6 TOD 21 13 VROR 5 20 CRDY 12 EOR 4 VOD 19 11 IFAULT 3 IOD 18 10 VSAG 2 LSD 17 IOR 9 1 FUP 16 VOR 8 0 IC
Default =
0x000001 (Status Register), 0x000000 (Mask Register)
The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit to reset. Writing a '0' to a bit will not change it's current state. The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the corresponding bit in the Status Register to activate the INT pin when the status bit is asserted. DRDY CRDY IOR VOR IROR VROR EOR FUP IFAULT VSAG TUP TOD Data Ready. During conversions, this bit will indicate the end of computation cycles. For calibrations, this bit indicates the end of a calibration sequence. Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate. Current Out of Range. Set when the Instantaneous Current Register overflows. Voltage Out of Range. Set when the Instantaneous Voltage Register overflows. IRMS Out of Range. Set when the IRMS Register overflows. VRMS Out of Range. Set when the VRMS Register overflows. Energy Out of Range. Set when PACTIVE overflows. Epsilon Updated. Indicates completion of a line frequency measurement and update of Epsilon. Indicates a current fault has occurred. See Section 5.6 Sag and Fault Detect Feature on page 19. Indicates a voltage sag has occurred. See Section 5.6 Sag and Fault Detect Feature on page 19. Temperature Updated. Indicates the Temperature Register has updated. Modulator oscillation detected on the temperature channel. Set when the modulator oscillates due to an input above full scale.
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VOD (IOD) Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscillates due to an input above full scale. The level at which the modulator oscillates is significantly higher than the voltage channel's differential input voltage (current) range. Note: The IOD and VOD bits may be `falsely' triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times. LSD Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON pin rises back above the high-voltage threshold (PMHI). Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Status Register has not been successfully read.
IC
6.1.12 Current and Voltage AC Offset Register ( VACoff , IACoff )
Address: 16 (Current AC Offset); 17 (Voltage AC Offset)
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default = 0x000000 The AC Offset Registers (VACoff, IACoff) are initialized to zero on reset, allowing for uncalibrated normal operation. AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration. These values may be read and stored for future system AC offset compensation. The value is represented in two's complement notation in the range of -1.0 VACoff, IACoff < 1.0, with the binary point to the right of the MSB
6.1.13 Operational Mode Register ( Mode )
Address: 18
23 15 7 XIDEL 22 14 6 IHPF 21 13 5 VHPF 20 12 4 IIR 19 11 3 E3MODE1 18 10 2 E3MODE0 17 9 E2MODE 1 POS 16 8 XVDEL 0 AFC
Default = 0x000000 E2MODE E2 Output Mode 0 = Sign of Active Power (default) 1 = Apparent Power Enables an extra sample of voltage channel delay. XVDEL and XIDEL can not be enabled at the same time. Enables an extra sample of current channel delay. XVDEL and XIDEL can not be enabled at the same time. Enables the High-pass Filter on the current channel. 0 = High-pass filter disabled (default) 1 = High-pass filter enabled
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VHPF Enables the High-pass Filter on the voltage channel. 0 = High-pass filter disabled (default) 1 = High-pass filter enabled Note: When either IHPF or VHPF are enabled, but not both, an all pass filter is applied to the opposite channel for phase-matching. IIR Enables the IIR compensation filters. 0 = IIR compensation filters enabled (default) 1 = IIR compensation filters disabled E3 Output Mode 00 = Reactive Power (default) 01 = PFMON 10 = Voltage sign 11 = Apparent Power Positive Energy Only. Negative energy pulses on E1 are suppressed. However, it will NOT suppress negative P register results. Enables automatic line frequency measurement and sets the frequency of the local sine/cosine generator used in fundamental/harmonic measurements. When AFC is enabled, the Epsilon register will be updated periodically.
E3MODE1:0
POS AFC
6.1.14 Temperature Register ( T )
Address: 19
MSB -(27) 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 LSB 2-16
T contains measurements from the on-chip temperature sensor. Measurements are performed during continuous conversions, with the default the Celsius scale (oC). The value is represented in two's complement notation and in the range of -128.0 T < 128.0, with the binary point to the right of the eighth MSB.
6.1.15 Average and Instantaneous Reactive Power Register ( QAVG , Q )
Address: 20 (Average Reactive Power) and 21 (Instantaneous Reactive Power)
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
The Instantaneous Reactive Power (Q) is the product of the voltage, shifted 90 degrees, and the current. The Average Reactive Power (QAVG) is Q averaged over N samples. The results are signed values with. The value is represented in two's complement notation and in the range of -1.0 < Q, QAVG< 1.0, with the binary point to the right of the MSB.
6.1.16 Peak Current and Peak Voltage Register ( Ipeak , Vpeak )
Address: 22 (Peak Currect) and 23 (Peak Voltage)
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
The Peak Current (Ipeak) and Peak Voltage (Vpeak) registers contain the instantaneous current and voltage with the greatest magnitude detected during the last computation cycle. The value is represented in two's complement notation and in the range of -1.0 Ipeak, Vpeak < 1.0, with the binary point to the right of the MSB.
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6.1.17 Reactive Power Register ( QTrig )
Address: 24
MSB 0 LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
The Reactive Power (QTrig) is calculated using trigonometric identities. (See Section 4.3 Power Measurements on page 14). The value is represented in unsigned notation and in the range of 0 S < 1.0, with the binary point to the right of the MSB.
6.1.18 Power Factor Register ( PF )
Address: 25
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Power Factor is calculated by dividing the Active (Real) Power by Apparent Power. The value is represented in two's complement notation and in the range of -1.0 PF< 1.0, with the binary point to the right of the MSB.
6.1.19 Apparent Power Register ( S )
Address: 27
MSB 0 LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Apparent power (S) is the product of the VRMS and IRMS, The value is represented in unsigned notation and in the range of 0 S < 1.0, with the binary point to the right of the MSB.
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6.1.20 Control Register ( Ctrl )
Register Address: 28
23 15 7 22 14 6 21 13 5 20 12 4 INTOD 19 11 3 18 10 2 NOCPU 17 9 1 NOOSC 16 8 STOP 0
Default = 0x000000 STOP Terminates the auto-boot sequence. 0 = Normal (default) 1 = Stop sequence Converts INT output pin to an open drain output. 0 = Normal (default) 1 = Open drain Saves power by disabling the CPUCLK pin. 0 = Normal (default) 1 = Disables CPUCLK Saves power by disabling the crystal oscillator. 0 = Normal (default) 1 = Disabling oscillator circuit
INTOD
NOCPU
NOOSC
6.1.21 Harmonic Active Power Register ( PH )
Address: 29
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
The Harmonic Active Power (PH) is calculated by subtracting the Fundamental Active Power from the Active (Real) Power. The value is represented in two's complement notation and in the range of -1.0 PH < 1.0, with the binary point to the right of the MSB.
6.1.22 Fundamental Active Power Register ( PF )
Address: 30
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
The Fundamental Active Power (PF) is calculated by performing a discrete Fourier transform (DFT) at the relevant frequency on the V and I channels. The results are multiplied to yield fundamental power. The value is represented in two's complement notation and in the range of -1.0 PH < 1.0, with the binary point to the right of the MSB.
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6.1.23 Fundamental Reactive Power Register ( QH ) Address: 31 (read only)
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Fundamental Reactive Power (QH) is calculated by performing a discrete Fourier transform (DFT) at the relevant frequency on the V and I channels. The value is represented in two's complement notation and in the range of -1.0 QH < 1.0, with the binary point to the right of the MSB.
6.1.24 Page Register
Address: 31 (write only)
MSB 26 25 24 23 22 21 LSB 20
Default = 0x00 Determines which register page the serial port will access.
6.2 Page 1 Registers
6.2.1 Temperature Gain Register ( TGain )
Address: 2
MSB 26 25 24 23 22 21 20 2-1 ..... 2-11 2-12 2-13 2-14 2-15 2-16 LSB 2-17
Default = 0x34E2E7 = 26.443169 Sets the temperature channel gain. Temperature gain (TGain) is utilized to convert from one temperature scale to another. The Celsius scale (oC) is the default. Values will be within in the range of 0 TGain < 128. The value is represented in unsigned notation, with the binary point to the right of bit 7th MSB. See Section 5.7 On-chip Temperature Sensor on page 19.
6.2.2 Temperature Offset Register ( TOff )
Address: 3
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default = 0xF3E7D0 = -0.094488 Temperature offset (Toff) is used to remove the temperature channel's offset at the zero degree reading. Values are represented in two's complement notation and in the range of -1.0 Toff < 1.0, with the binary point to the right of the MSB.
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6.3 Page 3 Registers
6.3.1 Voltage Sag and Current Fault Duration Registers ( VSAGDuration , ISAGDuration )
Address: 6 (Voltage Sag Duration); 10 (Current Fault Duration)
MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20
Default = 0x000000 Voltage Sag Duration (VSAGDuration) and Current Fault Duration (ISAGDuration) defines the number of instantaneous measurements utilized to determine a sag event. Setting these register to zero will disable this feature. The value is represented in unsigned notation. See Section 5.6 Sag and Fault Detect Feature on page 19.
6.3.2 Voltage Sag and Current Fault Level Registers ( VSAGLevel , ISAGLevel ) Address: 7 (Voltage Sag Level ); 11 (Current Fault Level )
MSB 0 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default = 0x000000 Voltage Sag Level (VSAGLevel) and Current Fault Level (ISAGLevel) defines the voltage level that the magnitude of input samples, averaged over the sag duration, must fall below in order to register a sag/fault condition. These value are represented in unsigned notation and in the range of 0 VSAGLevel < 1.0, with the binary point to the right of the third MSB. See Section 5.6 Sag and Fault Detect Feature on page 19.
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7. SYSTEM CALIBRATION
7.1 Channel Offset and Gain Calibration
The CS5463 provides digital DC offset and gain compensation that can be applied to the instantaneous voltage and current measurements, and AC offset compensation to the voltage and current RMS calculations. Since the voltage and current channels have independent offset and gain registers, system offset and/or gain can be performed on either channel without the calibration results from one channel affecting the other. The computational flow of the calibration sequences are illustrated in Figure 12. The flow applies to both the voltage channel and current channel. N + 30 conversion cycles to complete. For AC offset calibrations, the sequence takes at least 6N + 30 ADC cycles to complete, (about 6 computation cycles). As N is increased, the accuracy of calibration results will increase.
7.1.2 Offset Calibration Sequence
For DC and AC offset calibrations, the VIN pins of the voltage and IIN pins of the current channels should be connected to their ground reference level. (see Figure 13.)
External Connections
+
0V + AIN+
+
7.1.1 Calibration Sequence
The CS5463 must be operating in its active state and ready to accept valid commands. Refer to Section Section 5.15 Commands on page 23. The calibration algorithms are dependent on the value N in the Cycle Count Register (see Figure 12). Upon completion, the results of the calibration are available in their corresponding register. The DRDY bit in the Status Register will be set. If the DRDY bit is to be output on the INT pin, then DRDY bit in the Mask Register must be set. The initial values in the calibration registers do affect the results of the calibration results.
XGAIN
AIN-
-
-
CM + -
Figure 13. System Calibration of Offset
The AC offset registers must be set to the default (0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC offset calibration. Initiate a DC offset calibration. The DC offset registers are updated with the negative of the average of the instantaneous samples taken over a computational cycle. Upon completion of the DC offset calibration the DC offset is stored in the corresponding DC offset register. The DC offset value will be added to
to V*, I* Registers
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines the number of conversions performed by the CS5463 during a given calibration sequence. For DC offset and gain calibrations, the calibration sequence takes at least
In
Modulator
Filter
+
+
+
X
N
X
N
/N
+
+
+
VRMS*, IRMS* Registers
DC Offset*
Gain*
/N
AC Offset*
Inverse
-1
X
-1
X
0.6 RMS
* Denotes readable/writable register
Figure 12. Calibration Data Flow
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each instantaneous measurement to nullify the DC component present in the system during conversion commands. A typical rms calibration value which allows for reasonable over-range margin would be 0.6 or 60% of the voltage and current channel's maximum input voltage level. Two examples of AC gain calibration and the updated digital output codes of the channel's instantaneous data registers are shown in Figures 15 and 16. Figure 16
Before AC Gain Calibration (Vgn Register = 1)
250 mV
Sinewave
7.1.2.2 AC Offset Calibration Sequence
Corresponding offset registers IACoff and/or VACoff should be cleared prior to initiating AC offset calibrations. Initiate an AC offset calibration.The AC offset registers are updated with an offset value that reflects the RMS output level. Upon completion of the AC offset calibration the AC offset is stored in the corresponding AC offset register. The AC offset register value is subtracted from each successive VRMS and IRMS calculation.
0.9999... 0.92
Instantaneous Voltage Register Values
230 mV
INPUT 0V SIGNAL
-230 mV -250 mV
-0.92 -1.0000...
7.1.3 Gain Calibration Sequence
When performing gain calibrations, a reference signal should be applied to the VIN pins of the voltage and IIN pins of the current channels that represents the desired maximum signal level. Figure 14 shows the basic setup for gain calibration.
External Connections
R eference + Signal -
VRMS Register = 230/2 x 1/250 0.65054
After AC Gain Calibration (Vgn Register changed to approx. 0.9223)
250 mV
Sinewave
0.92231
230 mV
0.84853
Instantaneous Voltage Register Values
INPUT 0V SIGNAL
IN+
+
XG AIN
+ -
-230 mV -250 mV
-0.84853
-0.92231
VRMS Register = 0.600000
CM
+ -
IN-
-
Figure 15. Example of AC Gain Calibration
Before AC Gain Calibration (Vgain Register = 1)
Figure 14. System Calibration of Gain.
250 mV 230 mV
DC Signal
0.9999... 0.92
Instantaneous Voltage Register Values
For gain calibrations, there is an absolute limit on the RMS voltage levels that are selected for the gain calibration input signals. The maximum value that the gain registers can attain is 4. Therefore, if the signal level of the applied input is low enough that it causes the CS5463 to attempt to set either gain register higher than 4, the gain calibration result will be invalid and all CS5463 results obtained while performing measurements will be invalid. If the channel gain registers are initially set to a gain other then 1.0, AC gain calibration should be used.
INPUT 0 V SIGNAL
-250 mV
230 VRMS Register = 250 = 0.92
-1.0000...
After AC Gain Calibration (Vgain Register changed to approx. 0.65217)
250 mV 230 mV
DC Signal
0.65217
0.6000
Instantaneous Voltage Register Values
7.1.3.1 AC Gain Calibration Sequence
The corresponding gain register should be set to 1.0, unless a different initial gain value is desired. Initiate an AC gain calibration. The AC gain calibration algorithm computes the RMS value of the reference signal applied to the channel inputs. The RMS register value is then divided into 0.6 and the quotient is stored in the corresponding gain register. Each instantaneous measurement will be multiplied by its corresponding AC gain value.
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INPUT 0V SIGNAL
-250 mV
-0.65217
VRMS Register = 0.600000
Figure 16. Example of AC Gain Calibration
shows that a positive (or negative) DC level signal can be used even though an AC gain calibration is being executed.
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CS5463
However, an AC signal cannot be used for DC gain calibration. can be accomplished by restoring zero to the AC offset register and then perform an AC offset calibration sequence. The adjustment could also be done by multiplying the AC offset register value that was calculated in step 2 by the gain calculated in step 3 and updating the AC offset register with the product.
7.1.3.2 DC Gain Calibration Sequence
Initiate a DC gain calibration. The corresponding gain register is restored to default (1.0). The DC gain calibration averages the channel's instantaneous measurements over one computation cycle (N samples). The average is then divided into 1.0 and the quotient is stored in the corresponding gain register After the DC gain calibration, the instantaneous register will read at full-scale whenever the DC level of the input signal is equal to the level of the DC calibration signal applied to the inputs during the DC gain calibration.The HPF option should not be enabled if DC gain calibration is utilized.
7.2 Phase Compensation
The CS5463 is equipped with phase compensation to cancel out phase shifts introduced by the measurement element. Phase Compensation is set by bits PC[6:0] in the Configuration Register. The default value of PC[6:0] is zero. With MCLK = 4.096 MHz and K = 1, the phase compensation has a range of 2.8 degrees when the input signals are 60 Hz. Under these conditions, each step of the phase compensation register (value of one LSB) is approximately 0.04 degrees. For values of MCLK other than 4.096 MHz, the range and step size should be scaled by 4.096 MHz/(MCLK/K). For power line frequencies other than 60Hz, the values of the range and step size of the PC[6:0] bits can be determined by converting the above values from angular measurement into the time domain (seconds), and then computing the new range and step size (in degrees) with respect to the new line frequency.
7.1.4 Order of Calibration Sequences
1. If the HPF option is enabled, then any DC component that may be present in the selected signal path will be removed and a DC offset calibration is not required. However, if the HPF option is disabled the DC offset calibration sequence should be performed. When using high-pass filters, it is recommended that the DC Offset register for the corresponding channel be set to zero. When performing DC offset calibration, the corresponding gain channel should be set to one. 2. If there is an AC offset in the VRMS or IRMS calculation, then the AC offset calibration sequence should be performed. 3. Perform the gain calibration sequence. 4. Finally, if an AC offset calibration was performed (step 2), then the AC offset may need to be adjusted to compensate for the change in gain (step 3). This
7.3 Active Power Offset
The Power Offset Register can be used to offset system power sources that may be resident in the system, but do not originate from the power line signal. These sources of extra energy in the system contribute undesirable and false offsets to the power and energy measurement results. After determining the amount of stray power, the Power Offset Register can be set to cancel the effects of this unwanted energy.
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8. AUTO-BOOT MODE USING E2PROM
When the CS5463 MODE pin is asserted (logic 1), the CS5463 auto-boot mode is enabled. In auto-boot mode, the CS5463 downloads the required commands and register data from an external serial E2PROM, allowing the CS5463 to begin performing energy measurements. commands/data will determine the CS5463's exact operation, when the auto-boot initialization sequence is running. Any of the valid commands can be used.
8.2 Auto-boot Data for E2PROM
Below is an example code set for an auto-boot sequence. This code is written into the E2PROM by the user. The serial data for such a sequence is shown below in single-byte hexidecimal notation:
-64 00 00 60 Write Operation Mode Register, turn high-pass filters on. -44 7F C4 A9 Write value of 0x7FC4A9 to Current Gain Register. -48 FF B2 53 Write value of 0xFFB253 to Voltage Gain Register. -74 00 00 04 Unmask bit #2 (LSD) in the Mask Register. -E8 Start continuous conversions -78 00 01 00 Write STOP bit to Control Register, to terminate auto-boot initialization sequence.
8.1 Auto-boot Configuration
A typical auto-boot serial connection between the CS5463 and a E2PROM is illustrated in Figure 17. In auto-boot mode, the CS5463's CS and SCLK are configured as outputs. The CS5463 asserts CS (logic 0), provides a clock on SCLK, and sends a read command to the E2PROM on SDO. The CS5463 reads the user-specified commands and register data presented on the SDI pin. The E2PROM's programmed data is utilized by the CS5463 to change the designated registers' default values and begin registering energy.
VD+
EOUT1 EOUT2
Mech. Counter or Stepper Motor
5K
CS5463
SCLK SDI SDO MODE CS
5K
EEPROM
SCK SO SI CS
8.3 Which E2PROMs Can Be Used?
Several industry-standard serial E2PROMs that will successfully run auto-boot with the CS5461A are listed below:
* * * Atmel AT25010, AT25020 or AT25040 National Semiconductor NM25C040M8 or NM25020M8 Xicor X25040SI
Connector to Calibrator
Figure 17. Typical Interface of E2PROM to CS5463
Figure 17 also shows the external connections that would be made to a calibrator device, such as a PC or custom calibration board. When the metering system is installed, the calibrator would be used to control calibration and/or to program user-specified commands and calibration values into the E2PROM. The user-specified
These types of serial E2PROMs expect a specific 8-bit command (00000011) in order to perform a memory read. The CS5461A has been hardware programmed to transmit this 8-bit command to the E2PROM at the beginning of the auto-boot sequence.
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9. BASIC APPLICATION CIRCUITS
Figure 18 shows the CS5463 configured to measure power in a single-phase, 2-wire system while operating in a single-supply configuration. In this diagram, a shunt resistor is used to sense the line current and a voltage divider is used to sense the line voltage. In this type of shunt-resistor configuration, the common-mode level of the CS5466 must be referenced to the line side of the power line. This means that the common-mode potential of the CS5463 will track the high-voltage levels, as well as low-voltage levels, with respect to earth ground. Isolation circuitry is required when an earth-ground-referenced communication interface is connected. Figure 19 shows the same single-phase, two-wire system with complete isolation from the power lines. This isolation is achieved using three transformers: a general purpose transformer to supply the on-board DC power; a high-precision, low-impedance voltage transformer, with very little roll-off/phase-delay, to measure voltage; and a current transformer to sense the line current. Figure 20 shows a single-phase, 3-wire system. In many 3-wire residential power systems within the United States, only the two line terminals are available (neutral is not available). Figure 21 shows the CS5463 configured to meter a three-wire system with no neutral available.
5 k N
120 VAC
10 k
L
500 470 nF
500 470 F 0.1 F
10 0.1 F 14 VA+ 3 VD+
CS5463
9 CVR2 R1
VIN+
CVdiff R VCV+ 10 15 R IR Shunt R I+ C I+ 16 12 IIN+ C IC Idiff VINIIN-
17 PFMON 2 CPUCLK 1 XOUT 24
4.096 MHz Optional Clock Source
XIN
RESET CS SDI SDO SCLK INT E2 E1 AGND 13 DGND 4
19 ISOLATION 7 23 6 5 20 22
21
Serial Data Interface
VREFIN 11 VREFOUT
0.1 F
Note: Indicates common (floating) return.
Mech. Counter or Stepper Motor
Figure 18. Typical Connection Diagram (Single-phase, 2-wire - Direct Connect to Power Line)
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5 k
L
Voltage Transformer
12 VAC
120 VAC
10 k
N
200
200 0.1F 200F 14 VA+
10 0.1 F 3 VD+
12 VAC
CS5463
M:1 1k R V+ R VC Vdiff 10 VIN9 VIN+ PFMON CPUCLK XOUT 17 2 1 4.096 MHz 24 Optional Clock Source
1k
Low Phase-Shift Potential Transformer
XIN
N:1 1k RBurden 1k
Current Transformer
R IC Idiff
15
IIN-
RESET
19
16 RI+ 12
11
IIN+ VREFIN VREFOUT AGND 13
7 CS 23 SDI 6 SDO 5 SCLK 20 INT
E2 E1 22
21
Serial Data Interface
0.1 F
DGND 4
Mech. Counter or Stepper Motor
Figure 19. Typical Connection Diagram (Single-phase, 2-wire - Isolated from Power Line)
240 VAC 120 VAC 120 VAC
5 k L2 500 500 470 F 0.1 F 10 0.1 F
10 k
L1
N
470 nF Earth Ground
14 VA+
3 VD+
CS5463
9 VIN+ 17 PFMON 2 CPUCLK 1 XOUT 24
R3 R2 R1
R4
CIdiff
4.095 MHz Optional Clock Source
10
1k
VIN16 IIN+
XIN
R I+ RESET
C Idiff
19
RBurden
1k
15
R I-
IIN-
12 VREFIN 11 VREFOUT
AGND
7 CS 23 SDI 6 SDO 5 SCLK 20 INT
E2 E1 22 21
Serial Data Interface
0.1 F
13
DGND 4 Mech. Counter or Stepper Motor
Figure 20. Typical Connection Diagram (Single-phase, 3-wire)
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CS5463
5 k L2 1k 500 470 F 0.1 F 10 0.1 F 10 k
240 VAC
L1
235 nF
14 VA+
3 VD+
CS5463
9 R1 R2 R VCV+ CI+
VIN+
CVdiff
17 PFMON 2 CPUCLK 1 XOUT 24
4.096 MHz Optional Clock Source
10 16
VINIIN+
XIN
1k
R I+
ISOLATION
CIdiff
RBurden
1k
RESET CS SDI SDO SCLK INT
E2 E1
19 7 23 6 5 20 22
21
15
R I-
Serial Data Interface
IIN-
12 VREFIN 11 VREFOUT
AGND 13
0.1 F
DGND 4 Mech. Counter or Stepper Motor
Note: Indicates common (floating) return.
Figure 21. Typical Connection Diagram (Single-phase, 3-wire - No Neutral Available)
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10.PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 SEATING PLANE A
E e b2 SIDE VIEW
12 3
L
END VIEW
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4
MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4
NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150
Controlling Dimension is Millimeters. Notes: 3. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 4. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 5. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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11. ORDERING INFORMATION
Model Temperature Package
CS5463-IS CS5463-ISZ (lead free)
-40 to +85 C
24-pin SSOP
12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 240 C 260 C MSL Rating* 2 3 Max Floor Life 365 Days 7 Days
CS5463-IS CS5463-ISZ (lead free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
13. REVISION HISTORY
Revision Date Changes
A1 PP1
MAR 2005 AUG 2005
Advance Release First preliminary release, updated with most-current characterization data.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
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